Providing a clean power supply voltage is a crucial element of PCB and Package layout design. For the channel, however, approximations are often made as models for the power delivery network (PDN) and the signal nets are extracted separately. This separate extraction neglects the effects of coupling between the power-, ground- and signal nets. We therefore propose a more rigorous approach where only a single model for the channel is extracted that includes both the signal nets as well as the PDN, therefore allowing a SI/PI co-simulation with unprecedented accuracy.

With this eSeminar, learn about:

• A novel workflow that starts from a Package and PCB layout and yields a high fidelity circuit simulation with signal integrity and power integrity being considered concurrently in the same model.
• Guidelines on what material models should to be used and how to extract an equivalent circuit model that is reliable from DC up to multiple GHz.
• How to develop these guidelines on a test vehicle before applying them to a real-world model of a DDR4 memory channel that is represented by a 3D model of the Package as well as the system board. 

Watch the eSeminar: