FavoriteSimulation CST Studio Suite ​​​​​​​

One of my favorite simulations deals with undesired current return paths on Printed Circuit Boards.

Large current loops may lead to electromagnetic emissions and cause electromagnetic compatibility (EMC) or electromagnetic interference (EMI) effects. In many cases, such effects are discovered late in the design process, often after prototyping and during measurements in the lab.

Currents always flow in loops, from their source to an appliance or load and finally back to the source. In doing so, currents follow the path of the least impedance. If this path is interrupted because of slots or absent connecting structures (interlayer connections, vias, bypass capacitors, etc.), the current will use other (often undesired) return paths.

The two figures below compare the results of common mode current return paths for two different nets. Both nets are routed in an inner layer of the PCB. The adjacent reference plane is also shown in both figures. The first net runs from Port 2 to Port 3. Because the adjacent reference plane is almost perfectly smooth without any significant cutouts or slots, the common mode current can flow back directly beneath the signal net which minimizes the current loop.

A completely different situation can be seen with the second net that runs from Port 1 to Port 4. Owing to the fact that the adjacent reference plane is interrupted by a slot (the aim of which actually was to decouple the high speed electronics on the right from the rest of the PCB), the common mode return current can’t flow beneath the signal net but needs to find another way back to its source. This causes a significant large loop in the reference plane, thus yielding in radiated emission effects and infringing distance rules to other (susceptible) nets on the PCB.

I like this example because it is moderately simple, easy to understand and it demonstrates the full force of electromagnetic compatibility effects if design rules are disregarded or unintentionally overlooked.