Simulation of large scale EM-problems on the 3DEXPERIENCE® Cloud

The majority of CST Studio Suite users run simulations locally on their own dedicated license and hardware tailored to their average simulation need. For large EM Models and/or simulation peak demands the tailored configuration might fall short on the requirements. In this presentation, I present an overview of the simulation possibilities in the 3DEXPERIENCE Cloud. The full workflow will be demonstrated and the various license options will be discussed.

Presenter: Frank DEMMING-JANSSEN, SIMUSERV GmbH

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Power integrity simulations in the Pre-Layout design phase

Power integrity simulations allow to find design weaknesses at the early stages of the product development. With growing complexity of our designs, keeping the project timing becomes more and more challenging. That’s why it is important to optimize the design validation tasks in terms of timing. At this point the Pre-Layout simulations could play an important role. They could precede or run in parallel with the layout preparation and significantly improve the quality of the initial layout. In this presentation we demonstrate a simple and time efficient workflow for the power integrity simulation in the Pre-Layout phase. It allows to optimize the set of the decoupling capacitors for the first layout version, based on the IC design guideline information.

Presenter: Oleksandr TALALAEVSKYY, Continental Automotive GmbH

Misleading EM-Decoupling rules in PCB-design

Very often suppliers of integrated circuits publish application notes, where some decoupling rules are given, as ‘Decouple with 10nF, 100nF and 1μF in parallel and place the smaller capacitor closer to the supply pin.’ or ‘Use capacitors with low ESR for decoupling.’ This presentation takes a deeper look at some of these decoupling rules. By means of various examples it is shown, where and why these rules fail and why simulation should be used to find an optimum solution for decoupling.

Presenter: Joachim HELD, Siemens AG

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Modeling and Simulation of A DDR5 Prototype

As one of the most important computing connectivity, DDR (Double Data Rate) is an indispensable part of modern electronics. The launch of 5G network and Wi-Fi 6 accelerates the development of DDR standards, which focuses on higher storage capacity, internal and I/O speed (i.e. bandwidth). JEDEC DDR5 standard was released in July 2020. To address the challenges of DDR5's modeling and simulation, IBIS open forum published IBIS 7.1 in Dec 2021. In this presentation, we have a short review of DDR4 at first. The DDR5 challenges are discussed and presented with a prototype, which is created in Simulink based on IBIS standard and simulated with CST Studio Suit and Python script.

Presenter: Longfei BAI, Dassault Systèmes

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3D printed electronics and its ramification to the electronics design process

The new technology field of 3D printed electronics, or AME (Additively Manufactured Electronics), leads to a major change in the manufacturing paradigm for electronic structures. With the possibility to simultaneously process conductive and non-conductive material in one 3D printer, circuit designs are manufacturable, that would not have been realizable with traditional production methods. Since traditional tools for designing electronic structures are closely following the layer-based manufacturing paradigm, those tools are not suitable to design fully three-dimensional structures. One alternative that comes to mind are mechanical CAD tools, that inherently support the creation of 3D bodies. However, those tools are usually built for a purely mechanical context, and the import of external COTS (Commercial off-the-shelf) components, like transistors or chips is cumbersome. During the search for suitable design tools, the CST Studio Suite proved to already include many of the needed features. It supports the creation of 3D bodies and makes it easily possible to import electronic CAD data. Moreover, the availability of reliable electromagnetic field solvers makes it a valuable tool for the design and simulative validation of AME structures. This presentation gives insights on how the CST Studio Suite can be used to create AME parts and what additional features would further facilitate the life of an AME designer.

Presenter: Rolf BALTES, J.A.M.E.S. GmbH

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