Visteon | 100Base-T1 Ethernet: 3D Simulation and Layout Optimization Tips and Tricks | RUM 2022

Abstract

100Base-T1 Ethernet PHY is becoming the preferred choice for in-vehicle communication interface, but there are multiple contradicting guidelines on how to route and place it in order to meet tight requirements. Shall we cut GND under Common Mode Choke or not? Is it better to use tightly coupled or loosely coupled differential pair? What if we have via stubs? Those are only a few of the questions which every PCB designer would ask. The present article shows and analyzes distinct layout concepts, compares them back-to-back and checks how those impact some of the most critical interface parameters - Target Impedance, Differential Return Loss (Sdd11) and Mode Conversion (Sdc11). Multiple different 100Base-T1 ETH PHY topologies have been simulated in CST MWS, where not only S-parameters could be compared, but also surface currents and therefore the EMC Emissions impact can be seen as well. This paper gathers conclusions from all listed aspects for 100Base-T1 Ethernet Physical layer routing.

Presentation

Presenter Bio

Stiliyan Filipov received his Masters degree in electronics engineering from the Technical University of Sofia in 2010. Joined Visteon in 2009 and is focused on Signal Integrity, Power Integrity and EMC simulation and measurement activities since then. Co-author and presenter of an IEEE SI/PI/EMC chapter paper in 2014.

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