I am pleased to share the presentation "Maximizing the RF Performance of a DAC Front End" I held at the EuroMed SIMULIA Regional User Meeting on September 14, 2022, with you.

For the last 7 years, I have worked at D&P Electronic Systems in Frascati, Rome. In his position, I focus on RF/IF, where I deal with the following:

• Signal/Power Integrity analysis with CST Studio Suite
• RF budget analysis for RF front end with MATLAB®/Simulink®
• Hardware Test Validation with RF instruments such as Spectrum Analyzer, RF generator, Power Meter, Vector Network Analyzer
  
  

Abstract:

Most RF interfaces are designed to be either 50 Ω single-ended or 100 Ω differential. With the latest RF high-speed D/A converter with sampling operating up to 5 Hz or higher, the parasitic on the silicon die and the laminate package causes the input or output impedance to vary significantly over frequency. Because of this variation in impedance vs. frequency, it is necessary to design the printed circuit board (PCB) carefully to obtain the optimum performance in the particular band of interest. 
CST Studio Suite was used to simulate and optimize the s sampling clock chain and the output signal generation for the RF DAC AD9164 by Analog Devices. 
For the sampling clock interface, the simulations in CST Studio Suite had the aim of optimizing the 
Return Loss trend in correspondence with the input coaxial SM connector. 
For the DAC output interface, the simulations in CST Studio Suite aimed to reduce the ripple of the output power in the band of interest. A new PCB design for the DAC output stage was implemented to maximize the output power and improve the flatness in the channel DAC response. 

Here now the PDF slides and recording (in Italian with subtitles) of my presentation:

Slide deck

Recording — Italian with subtitles

@MR​​​​​​, 
Focal Point RF/IF Activities at D&P Electronic Systems  

RUM2022 ​​​​​​​RUM2022-EuroMed ​​​​​​​ CST Studio Suite ​​​​​​​