RUM2021 RUM2021-EuroCentral CustomerPresentation
Abstract:
Power integrity simulations play an important role in the product development process. The IR drop (DC Power integrity) simulations show us how much voltage drop occurs in the layout between the Voltage Source (Battery, Buck Converter etc.) and a sink IC. Such checks are performed to ensure that the sink IC gets enough voltage. For a correct usage of this workflow it is necessary to correctly set up the power/ground nets. A lot of Source ICs use the cooling plane area underneath the package as a reference GND for the better heat transfer. In some cases, the default layout import from the ODB file leads to the wrong GND pin pads assignment at the cooling plane. This causes the increased IR drop in the GND system correspondingly. In this talk we report the modified IR drop workflow that allows to redefine GND pins pads at the cooling plane area. The modified workflow gives us more accurate simulation results.
Speaker Info:
Institution | Subject/Position | Dates | Comments |
Taras Shevchenko National University of Kiev | Radiophysics and electronics (Master Diploma) | 2009-2011 | Diploma Thesis: Microwave properties of the periodic permalloy nanostructures |
Institute of physics of the materials, University of Porto, Portugal. | Magnetism and electronics (Visiting scientist) | 2012-2013 | Investigation of the microwave properties of the multilayered ferromagnetic structures using the VNA technique |
University of Regensburg/ University of Leeds | Magnetism (Ph.D) | 2013 -2017 | Thesis: Dynamic measurements of spin Hall angle. |
Continental Automotive, Regensburg | EMC simulations / Design support | 2017 -> | Electromagnetic compatibility simulations |
