This sample scenario shows how integrated circuit design companies can use our semiconductor solutions based on the 3DEXPERIENCE platform.

It enables significant advancements with respect to issue and defect management, distributed design team collaboration and managing and maximizing reuse in design and engineering, as well as IP management.

1. SoC BOI configuration

1. Search & Select existing IP to reuse
2. Review Issues / Defects / Dispositions and Impact Analysis
3. Create new SoC: Skipped in this video
4. Search & Select SoC to Reuse
5. Change SoC + integrate existing IP

2. New IP Development Request with Cadence Virtuoso

1. Search & Select existing IP to reuse
2. IP Request
3. Create IP and export to design environment
4. Create work area in engineering design environment
5. Launch virtuoso & Modify the design
6. Publish (Synchronize) the design to 3DEXPERIENCE
7. Review Synchronized IP on 3DEXPERIENCE
8. Check New IP release and Complete the IP Request

3. IP Access request and Modify the IP with sda

1. IP Access request
2. IP Access approve
3. Export IP to design environment
4. Launch sda, IP design update, check in and synchronize
5. Review updated IP on 3DEXPERIENCE