Question regarding SysML signals between nested blocks

 

 

 

I have a simple model:

 

 

The behavior I see when simulating the model is that the signal correctly goes from A to B, from C to D, but no signal is send from E to F (I have verified the connector configuration in the SD).

 

I would like to know if this behavior expected, or if it's due to incorrect or incomplete model.

Note:

  • Technically I could sent to the port instead, but this doesn't scale for real models.
  • Adding delegate ports does not solve the problem, since there would be no connector from E to F to refer to in the message from E to F.

 

Thank you for you help (also thanks for the MBSE Insight authors, extremely helpful videos).